Job statistics for Functional Safety Architect
- Days open
- 16 days
- Expected tenure
- 7 years
- Estimated salary
- $44,000
- Based on Senior seniority, the Semiconductor industry and India market rates.
Technologies used5 tools
Named in this posting. Hover a tool for what it is; the link finds other roles that use it.
Current safety team2 tracked professionals
- By function
- 1 senior / lead, 1 leadership
- Hiring now
- 1 open safety role on FSTalent, including this one
Counts of functional safety professionals FSTalent tracks at Altera and roles it is hiring for. It is a sample of public profiles, not the full headcount.
- Ankur M — Sr Manager, Functional Safety
- Shahram Jamshidi — Head of Product Security, Privacy and Safety Assurance
Median tenure at company1.8 years
Median time employees have been at Altera, from its LinkedIn company page (as of 2026-09).
Functional Safety Architect
Job description
Job Description
Altera is a global leader in programmable logic and semiconductor solutions. We design cutting-edge technologies that enable innovation across AI, networking, data centers, and embedded applications. Our team is passionate about pushing the boundaries of what’s possible in silicon design.
Become a member of our world-class SoC architecture and development team!
Position Overview
You will collaborate with architects, IP owners, RTL design engineers, physical design, firmware and verification teams to deliver critical safety collaterals ensuring end goal of achieving successful functional safety certification.
Key Responsibilities
- Collaborate with the Architects, Silicon Design, Software teams to architect new safety concepts and safety mechanism features and guide future development.
- Perform safety analyses (FTA, , DFA methodologies) against CCF, CF to ensure FFI, independence & Fault tolerance requirements are met.
- Define safe architecture patterns (lockstep CPUs, ECC memories, watchdogs, redundancy).
- Review and contribute to writing safety requirement specifications with FSEs.
- Guide teams on /SIL decomposition, fault tolerance, diagnostics coverage, etc.
- Review hardware/software safety designs for compliance and feasibility.
- Collaborate with design verification teams to define safety strategy (fault injection, fault simulation, test methodologies).
- Ensure achievement of diagnostic coverage metrics (SPFM, LFM, PMHF).
- Document and present defensible safety case evidences aligned with IEC 61508, ISO 26262 ensuring clarity and traceability for stakeholders and assessors.
Minimum Requirements
- Bachelor’s or Master’s degree in Electrical Engineering or equivalent
- BS + 10 Years of silicon industry experience or MS + 8 years of silicon industry experience
- Relevant safety professional certifications (Eg. FSCP, FS Professional license)
- Experience in certifying devices from concept through certification for ASICs/PLDs/CPUs with EXIDA, TUeV or Equivalent
- Skilled with SysML, FMEA/FMEDA, FTA, HAZOP and requirements-management tooling (e.g., Jama).
- Demonstrated strong ability to move seamlessly between levels of abstraction – from system to the “nuts and bolts” implementation
- Excellent written & oral communication skills to construct clear, evidence-based safety arguments and build trust in safety cases with both internal and external stakeholders
Preferred Qualifications
- Familiarity with RTL coding and simulations/debug of SoC Architectures.
- Desire to develop deep understanding of end user needs and engagement with customers to enable use of SoCs in safety design applications
- Desire to commit and follow through on complex, multi-year programs
- Ability to resolve complex issues in creative, efficient, and effective ways
- Be self-driven and result oriented
- Desire to work in a fast-paced environment
Job Type
Regular
Shift
Shift 1 (India)
Primary Location
Bengaluru, Karnataka, India
Legal and equal opportunity notices
We are seeking a highly motivated & passionate for safety, Architect to join our semiconductor architecture design team. In this role, you will own the device safety architecture and lead the efforts to achieve safety goals by developing technical safety concepts including safety mechanisms derived from safety analyses; and allocating decomposed safety requirements to each IP sub-blocks for next-generation semiconductor devices.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.